CMOS biotechnology for in vivo monitoring and in vitro diagnostics

• Jun-Chau Chien
• • National Taiwan University, Taiwan

• Date: November 08, 2022 (Tuesday)
• Time: 16:00 - 16:25 (UTC+8)
• Room: Song Bo 松柏廳, 10F

“Continuous” monitoring of specific biomarkers in real-time offers longitudinal information that can enable not only rapid medical decision-making but also early disease detection. As opposed to the current end-point diagnostics approaches, such a continuous-monitoring capability introduces a new dimension in achieving precision medicine and precision health. In this talk, I will present my research contributions toward this goal. Specifically, my research harvests the power of CMOS integrated circuits, applied physics, and advanced biotechnology to address biosensing requirements on sensitivity, specificity, throughput, multiplexing, device miniaturization, and system scaling. I will focus on two developed technology platforms: (1) an electrochemical-sensing wireless implant for in vivo monitoring of small molecules using reagentless structure-switching “aptamers” and (2) a cytometry-on-CMOS platform for high-throughput studies of the electromagnetic signatures at GHz frequencies. The former has broad applications including precision drug dosing and early disease detection whereas the later has the potentials for sensing circulating-tumor-cells in blood. I will also present my recent activity in developing high-resolution intraoperative imaging tools.

Jun-Chau Chien received the B.S. and M.S. degrees from National Taiwan University in 2004 and 2006, and Ph.D. degree from University of California, Berkeley, in 2015. He received the postdoctoral training from 2017–2018 at Stanford University and served as a Research Engineer from 2018-2021, also at Stanford University. He joins National Taiwan University in February 2021 and is currently an Assistant Professor at Department of Electrical Engineering. His research focuses on CMOS-based microsystems for in vitro and in vivo biosensing and high-speed millimeter-wave and mixed-signal circuits and systems. He is currently serving on ISSCC International Technical Program Committee.

Fast Battery Charging Technology from Integrated Circuits to Systems

• Kunhee Cho
• • Kyungpook National University, Korea

• Date: November 08, 2022 (Tuesday)
• Time: 16:25 - 16:50 (UTC+8)
• Room: Song Bo 松柏廳, 10F

Fast charging technology is gaining popularity to alleviate battery capacity limits and fulfill the user’s convenience. To achieve faster charging, not only power efficient circuit designs but also advanced architectures have become crucial for efficient power conversions in the battery charger system. This talk will overview the fast charging technology in the recent industry in the aspect of integrated circuits and systems. Further, advances and challenges of battery chargers will be introduced to address the trend of battery charger markets.

Kunhee Cho received the B.S. and M.S. degrees in electrical and electronic engineering from Yonsei University, Seoul, South Korea, in 2007 and 2009, respectively, and the Ph.D. degree in electrical and computer engineering from the University of Texas at Austin, Austin, TX, USA, in 2016.

From 2009 to 2012, he was with the Fairchild Semiconductor, Bucheon, South Korea, where he designed power management integrated circuits (ICs). In 2015 and 2016, he was a Graduate Research Intern with the Texas Instruments Incorporated, Dallas, TX, USA, in the low-power RF team. From 2017 to 2019, he was with Qualcomm Technologies Incorporated, Santa Clara, CA, USA, where he designed power management ICs for battery charger systems. He is currently an Assistant Professor at the School of Electronics Engineering, Kyungpook National University, Daegu, South Korea. His research interests include power management ICs, gate drivers, class-D amplifiers, and RF power amplifiers.

Frequency Synthesis Techniques and Low Flicker Noise Oscillators Towards Sub-50fs Jitter

• Yizhe Hu
• • University of Science and Technology of China, China

• Date: November 08, 2022 (Tuesday)
• Time: 16:50 - 17:15 (UTC+8)
• Room: Song Bo 松柏廳, 10F

A frequency synthesizer of ultralow jitter (e.g., sub-50fs) is a key block to enable 5G/6G wireless and other high-speed communication standards. It relies on the new architectures of frequency synthesizers and low flicker phase noise oscillators (especially in advanced CMOS). In this talk, we introduce the recent advancements in low-flicker phase noise oscillators and summarize two main routes towards ultralow jitter: 1) high-bandwidth PLLs with high phase-detector gain (with emphasis on all-digital PLLs), and 2) injection locking (IL) or recently proposed charge-sharing locking (CSL). It is expected to serve a unified guide on achieving sub-50 fs jitter requirements.

Yizhe Hu (Member, IEEE) was born in Chenzhou, Hunan, China, in 1990. He received the B.Sc. degree (summa cum laude) in microelectronics from Harbin Institute of Technology, Harbin, China, in 2013, and the Ph.D. degree in microelectronics from University College Dublin, Dublin, Ireland, in 2019. From 2013 to 2014, he was a Post-Graduate Researcher with Fudan University, Shanghai, China, where he was involved in the radio-frequency integrated circuits (RFICs) design. From 2016 to 2017, he was consulting for the PLL Group of HiSilicon, Huawei Technologies, Shenzhen, China, designing 16-nm digitally controlled oscillators (DCOs) and all-digital phase-locked loops (ADPLLs). From 2018 to 2022, he had been consulting for the Mixed-Signal Design Department, TSMC, Hsinchu, Taiwan, for a new type of PLL design in 5-nm CMOS. From 2019 to 2020, he was a Post-Doctoral Researcher with Prof. Staszewski’s Group, University College Dublin. From 2019 to 2022, he was a Principal Investigator with the Microelectronic Circuits Centre Ireland (MCCI), Dublin. Since 2022, he has been a Professor (tenure-track) with University of Science and Technology of China, Hefei, China. His research interests include digital-RF/mm-Wave integrated circuits and systems (digital-RF) for wireless communications.

Wireless Transceivers for Future 6G Satellite Constellation

• Atsushi Shirane
• • Tokyo Institute of Technology, Japan

• Date: November 08, 2022 (Tuesday)
• Time: 17:15 - 17:40 (UTC+8)
• Room: Song Bo 松柏廳, 10F

The talk will focus on research and developing wireless transceivers and integrated circuits for wireless communications that can operate in space to realize low earth orbit small satellite constellations, which is expected to be a future 6G communication network. The key to realizing such a network is to reduce the size and weight of the radio equipment mounted on the satellite, make it highly radiation tolerant, and reduce its power consumption. The talk will introduce the actual satellite wireless transceiver and circuit design, which will be launched.

Atsushi Shirane received the B.E. degree in electrical and electronic engineering and the M.E. and Ph.D. degrees in electronics and applied physics from the Tokyo Institute of Technology, Tokyo, Japan, in 2010, 2012, and 2015, respectively. From 2015 to 2017, he was with Toshiba Corporation, Kawasaki, Japan, where he developed 802.11ax Wireless LAN RF transceiver. From 2017 to 2018, he was with Nidec corporation, Kawasaki, Japan, where he researched on intelligent motor with wireless communication. He is currently an Associate Professor in Laboratory for Future Interdisciplinary Research of Science and Technology, Institute of Innovative Research, Tokyo Institute of Technology. His current research interests include RF CMOS transceiver for IoT, 5G, and satellite communication and wireless power transfer. He is a member of the IEEE Solid-State Circuits Society, and the Institute of Electronics, Information and Communication Engineers (IEICE).