A 1-to-4b 16.8-POPS/W 473-TOPS/mm2 6T-Based In-Memory Computing SRAM in 22nm FD-SOI with Multi-Bit Analog Batch-Normalization

• Adrian Kneip
• • Université Catholique de Louvain

• Date: November 09, 2022 (Wednesday)
• Time: 11:00 - 11:20 (UTC+8)
• Room: Song Bo 松柏廳, 10F

Computing in-memory (CIM) is rapidly becoming an enticing solution to accelerate convolutional neural networks (CNNs) at the edge. Yet, low-precision current-based CIM-SRAMs face severe SNR degradation due to numerous analog non-idealities and high quantization noise when performing analog-to-digital conversion prior to digital batch-normalization (DBN). In this paper, we propose a dual-supply 1-to-4b CIM-SRAM macro in 22nm FD-SOI using 6T foundry bitcells, co-designed with a CIM-aware CNN training framework to overcome these challenges. The macro includes a multi-bit analog BN (ABN) unit combined with self-calibrating dual-phase sense-amplifiers (SCDP-SAs). Measurement results show peak 1b-normalized power and area efficiencies of 16.8POPS/W and 473TOPS/mm2 at 0.4/0.8V supply and 100MHz, surpassing existing low-precision designs.

Adrian Kneip received the M.Sc. degree in Electrical Engineering from the Université catholique de Louvain (UCLouvain), Louvain-la-Neuve, Belgium, in 2019. He is currently working there towards the PhD degree with the Electronics Circuits and Systems group led by Prof. David Bol. His research interests include the modelling and design of mixed-signal ultra-low power systems and machine-learning hardware, with special dedication to SRAM memories and in-memory computing. He also serves as IEEE Student Branch Representative for the Benelux Section since 2020.

A 10.4-ENOB 0.92-5.38 µW Event-Driven Level-Crossing ADC with Adaptive Clocking for Time-Sparse Edge Applications

• Jonah Van Assche
• • Katholieke Universiteit Leuven

• Date: November 09, 2022 (Wednesday)
• Time: 11:20 - 11:40 (UTC+8)
• Room: Song Bo 松柏廳, 10F

For sensor applications with time-sparse signals such as ECGs, neural action potentials, etc., event-driven level-crossing ADCs (LCADCs) can directly compress the sensor signal while sampling it, leading to potential large system power savings in data processing and/or transmission. The LCADCs reported in literature, however, do not achieve good power efficiencies and do not achieve a high ENOB. This paper proposes a novel event-driven LCADC that uses clocked comparators and event-driven adaptive clocking to overcome the high power consumption and signal-dependent distortion of previous LCADCs. The ADC obtains 10.4 ENOB and shows dynamic power consumption (5.38 μW for a 15 kHz full-scale sine wave, only 0.92 μW for a typical ECG signal). The peak Walden FOM of the ADC is 138 fJ/conv, an improvement of 35% in power efficiency beyond the state of the art. For an ECG application, the IC achieves a data reduction of 30%, clearly indicating that the LCADC can achieve a large power reduction at system level.

Jonah Van Assche received the M.Sc. degrees in nanotechnology from Katholieke Universiteit Leuven (KU Leuven), Leuven, Belgium and from Kungliga Tekniska högskolan Stockholm (KTH Stockholm), Stockholm, Sweden, in 2018. He is currently working toward the Ph.D. degree in electrical engineering at the MICAS research group at KU Leuven, under the supervision of Prof. Georges Gielen. His current research interests include mixed-signal circuits for adaptive sensor readout, sense -and compress front-ends and circuits for biomedical sensors.

A 28nm 6.5-8.1GHz 1.16mW/Qubit Cryo-CMOS System-on-Chip for Superconducting Qubit Readout

• Alican Caglar
• • imec, Vrije Universiteit Brussel

• Date: November 09, 2022 (Wednesday)
• Time: 11:40 - 12:00 (UTC+8)
• Room: Song Bo 松柏廳, 10F

This paper presents a 28 nm cryo-CMOS system-on-chip (SoC) for the dispersive readout of superconducting qubits operating between 6.5-8.1 GHz at 4 K. The SoC includes a quadrature VCO and a full zero-IF transmitter and receiver chain, including 200 MS/s 7-bit DACs, ADCs, and digital. It can generate pulses up to 640 ns duration, and it attains a very low-power readout operation (9.8 mW) compared to its counterparts with 0.5-0.6 dB noise figure, 65-89 dB gain, and -71 dBm maximum TX output power at 4 K. Furthermore, with its duty-cycled mode, the SoC reduces the average power dissipation for the readout application.

Alican Caglar received the B.Sc. and M.Sc. degrees at the Department of Electronic Engineering from Istanbul Technical University, Turkey, in 2015 and 2019, respectively. He worked as an embedded software engineer at Netas, Turkey from 2015 to 2016. He is currently pursuing the Ph.D. degree at the Department of Electronics and Informatics (ETRO), Vrije Universiteit Brussel, Belgium, in collaboration with imec, Leuven, Belgium. His research is focused on cryo-CMOS circuits for quantum computing applications.

Fully Integrated Si:HfO₂ Negative Capacitance 2D-2D WSe₂/SnSe₂ Subthermionic Tunnel FETs

• Sadegh Kamaei
• • École Polytechnique Fédérale de Lausanne

• Date: November 09, 2022 (Wednesday)
• Time: 12:00 - 12:20 (UTC+8)
• Room: Song Bo 松柏廳, 10F

We report the first experimental demonstration and performance characterization of a fully integrated negative capacitance (NC) WSe₂/SnSe₂ p-type Tunnel FETs (TFETs), validating the use of NC as a technology booster to achieve a significantly improved sub-thermionic electronic switch. A sub-30 mV/dec point SS and 50 mV/dec average swing over 2.5 decades of current with I_on/I_off > 104 are reported. Moreover, the low-slope region and I₆₀ figures of merit are extended by 1.5 orders of magnitude due to the internal voltage amplification of the NC. Importantly, the supply voltage is reduced by 0.3 V by NC to achieve the same output current, I_on. Our results fully demonstrate the combined merits of band-to-band-tunneling in 2D/2D WSe₂/SnSe₂ heterostructure with NC as a universal performance booster for 2D Tunnel FETs, offering to future 2D platforms a path towards improved energy efficiency.

Sadegh Kamaei received his M.Sc. degree and first rank award in Electrical and Computer Engineering from University of Tehran in 2018. He is currently a Ph.D. Candidate in the Nonoelectronic devices laboratory (Nanolab) group at the Department of Electrical and Micro Engineering, EPFL lausanne. In 2020, he received an award as a PhD of the year of the microelectronic doctoral program. His research interests include 2D materials, energy efficient devices, negative capacitance, neuromorphic and ferroelectric materials.

A K-Band Gilbert-Cell Frequency Doubler with Self-Adjusted 25% LO Duty-Cycle in SiGe BiCMOS Technology

• Lorenzo Piotto
• • University of Pavia

• Date: November 09, 2022 (Wednesday)
• Time: 12:20 - 12:40 (UTC+8)
• Room: Song Bo 松柏廳, 10F

This paper presents a novel frequency doubler that further enhances the superior performance of solutions based on the Gilbert-cell mixer. A novel scheme is proposed to operate the cell with a 25% LO duty-cycle. This technique boosts the conversion gain by generating a square-wave like output current. Moreover, the use of a quadrature generation block, commonly adopted in mixer-based frequency doublers, is not required, thus improving the operation bandwidth. The duty-cycle is automatically regulated by a low-frequency feedback loop which ensures optimal operation against input power and PVT variations. The performance of a test chip in a SiGe – BiCMOS process is presented. With a low supply voltage of 1.5V, the chip achieves 6 dB conversion gain, 5.7dBm peak Psat and 17% power efficiency at 20 GHz. The doubler delivers Psat >3dBm over more than one octave bandwidth. Experimental results compare favorably against previously reported frequency doublers in the same frequency range.

Lorenzo Piotto was born in Padua, Italy, in 1994. He received B.Sc. and M.Sc. degrees in Electronics Engineering at the University of Padua in 2016 and 2018, respectively. From 2019 to 2020 he was with Infineon Technologies Austria, Villach, where he worked on the design and verification of mm-Wave blocks for wireless communication.

In 2021 he joined the University of Pavia where he is working towards his Ph.D. His current research interest is in the design of building blocks for high data-rate backhaul communications operating in D-band.