3D IC and Advanced Packaging

• Kuan-Neng Chen
• • National Yang Ming Chiao Tung University, Taiwan

• Date: November 09, 2022 (Wednesday)
• Time: 11:00 - 11:25 (UTC+8)
• Room: Auditorium 國際會議廳, 10F

3DIC and advanced packaging have been acknowledged as a significant element to keep the technology and performance innovation of microelectronics. Within the scope, heterogeneous integration and chiplet schemes can effectively overcome the challenges we have encountered and provide news options which may be difficult in the past from the design point view. This presentation will cover the introduction of 3DIC and advanced packaging, different schemes, and key technologies to achieve these schemes. Current applications, status, challenges, and outlook will also be mentioned.

Dr. Kuan-Neng Chen received his Ph.D. degree in Electrical Engineering and Computer Science, and his M.S. degree in Materials Science and Engineering, both from Massachusetts Institute of Technology (MIT). He is currently Associate Dean of International College of Semiconductor Technology, and Chair Professor of Institute of Electronics in National Yang Ming Chiao Tung University. Prior to the faculty position, he was a Research Staff Member at the IBM Thomas J. Watson Research Center.

Dr. Chen is the recipient of IEEE EPS Exceptional Technical Achievement Award, IMAPS William D. Ashmon – John A. Wagnon Technical Achievement Award, National Industrial Innovation Award, MOST Outstanding Research Award (2 times), MOST Futuristic Breakthrough Technology Award, NYCU Outstanding Industry-Academia Cooperation Achievement Awards (6 times), CIE Outstanding Professor Award, CIEE Outstanding Professor Award, and IBM Invention Achievement Awards (5 times). He has authored more than 300 publications, including 3 books and 6 book chapters, and holds 84 patents. He was Guest Editor of MRS Bulletin and IEEE Transactions on Components, Packaging, and Manufacturing Technology. He served as General Chair of IEEE IITC and Program Co-Chair of IEEE IPFA, and committee member of IEDM, IEEE 3DIC, IEEE SSDM, IEEE VLSI-TSA, and IMAPS 3D Packaging. Dr. Chen is a Fellow of National Academy of Inventors (NAI), IEEE, IET, and IMAPS, and a member of Phi Tau Phi Scholastic Honor Society.

In addition to his faculty position, Dr. Chen is currently Program Director of Micro-Electronics Program in Ministry of Science and Technology in Taiwan, Specially Appointed Professor of Tokyo Institute of Technology (Tokyo Tech) and Adjunct R&D Director in Industrial Technology and Research Institute (ITRI). Dr. Chen’s current research interests are three-dimensional integrated circuits (3D IC), advanced packaging, and heterogeneous integration.

Circuits and packaging systems for security chips

• Makoto Nagata
• • Kobe University, Japan

• Date: November 09, 2022 (Wednesday)
• Time: 11:25 - 11:50 (UTC+8)
• Room: Auditorium 國際會議廳, 10F

The security and trust of semiconductor integrated circuit (IC) chips are highly requested. Recent advancements in circuits and packaging systems of IC chips for security applications are highlighted about the countermeasures against physical implementation attacks. The Si-substrate of a CMOS wafer is post-processed to embed metal wirings on its backside to form passive components and to function with ICs on the frontside. Test vehicles with Si-backside buried metal (BBM) are manufactured in 0.13 um CMOS, assembled in flip-chip packaging and in three-dimensional chip stacking, and demonstrated for protection of crypto ICs against electromagnetic and power side channel attacks.

Makoto Nagata (Senior Member, IEEE) received the B.S. and M.S. degrees in physics from Gakushuin University, Tokyo, Japan, in 1991 and 1993, respectively, and the Ph.D. degree in electronics engineering from Hiroshima University, Hiroshima, Japan, in 2001. He was a Research Associate at Hiroshima University from 1994 to 2002, an Associate Professor at Kobe University, Kobe, Japan, from 2002 to 2009, where he was promoted to a Full Professor in 2009. He is currently a Dean and Professor with the Graduate School of Science, Technology and Innovation, Kobe University.

His research interests include design techniques targeting high-performance mixed analog, RF and digital VLSI systems with particular emphasis on power/signal/substrate integrity and electromagnetic compatibility, testing and diagnosis, three-dimensional system integration, as well as their applications for hardware security and safety, and cryogenic electronics for quantum computing.

Dr. Nagata is a Senior Member of IEICE. He has been a member of a variety of technical program committees of international conferences, such as the Symposium on VLSI Circuits (2002–2009), Custom Integrated Circuits Conference (2007–2009), Asian Solid-State Circuits Conference (2005–2009), International Solid-State Circuits Conference (2014-2022), European Solid- State Circuits Conference (since 2020), and many others. He chaired the Technology Directions subcommittee for International Solid-State Circuits Conference (2018-2022) and now serves for an Executive Committee Member. He was the Technical Program Chair (2010–2011), the Symposium Chair (2012–2013), and an Executive Committee Member (2014–2015) for the Symposium on VLSI circuits. He was the IEEE Solid-State Circuits Society (SSCS) Distinguished Lecturer (DL) (2020-2021) and also the IEEE SSCS Kansai Chapter Chair (2017–2018). He is currently an AdCom Member of the IEEE SSCS (since 2020), and an associate editor for IEEE Transactions on VLSI Systems (since 2015).

Neuron-inspired wireless telemetry for implantable neural interfaces

• Yao-Hong Liu
• • IMEC, Netherlands

• Date: November 09, 2022 (Wednesday)
• Time: 11:50 - 12:15 (UTC+8)
• Room: Auditorium 國際會議廳, 10F

The human brain has up to 80 billion of neurons, and currently we still have very little idea how our brains function. With the advancement in high-density intra-cortical micro-electrode arrays (MEAs), electrical activities of neurons can be recorded with sub-millisecond temporal resolution and 10’s of µm spatial resolution. They have become the most widely adopted method in neuroscience experiments and neuro-therapeutics at the moment. However, one of the key challenges yet to overcome, is to have a high-bandwidth, miniature and low-energy wireless telemetry, such that these MEAs can be chronically implanted without infection risks. Such MEAs produces a huge amount of data which need to be wirelessly transferred across layers of tissue without introducing heating, but miniature neural implants have very limited resource to support energy-consuming data transmission. In this talk, we will discuss recent advancements in high-bandwidth and miniature wireless telemetry for future implantable brain-computer interfaces.

Yao-Hong Liu (S’04-M’09-SM’17) is currently Scientific Director in imec, and a distinguished research associate in Technical University Eindhoven. He is a recipient of European Research Council (ERC) Consolidator grant. His current research focuses on wireless technologies for implantable brain-computer interfaces and IoT.

Dr. Liu received his Ph.D. degree from National Taiwan University, Taiwan, in 2009. He was with Terax, Via Telecom (now Intel), and Mobile Devices, Taiwan, from 2002 to 2010, developing wireless transceiver ICs. Since 2010, he joined imec, the Netherlands, and is leading the research of the ultra-low power ASIC design. He served as a technical program committee of IEEE ISSCC and is currently a steering committee member of IEEE RFIC symposium.

Cryogenic CMOS for Quantum Computing

• Stefano Pellerano
• • Intel Labs, USA

• Date: November 09, 2022 (Wednesday)
• Time: 12:15 - 12:40 (UTC+8)
• Room: Auditorium 國際會議廳, 10F

Scaling a fault-tolerant quantum computer to millions of qubits required for running a practical algorithm is a daunting challenge. Substantial innovation is required in qubit fabrication, integration and control. CMOS integrated circuits operating at cryogenic temperature down to 4K can offer significantly higher system integration and enable scalability for future quantum computers. Complex System-on-Chips (SoCs) with digital, analog and RF capabilities can be integrated with sufficiently low power consumption to be compatible with the requirements of dilution refrigerators. This talk introduces some of the fundamental concepts of quantum computing with a focus on the control electronics and the benefits of cryogenic CMOS. It then gives an overview of two Intel cryogenic SoCs (Horse Ridge 1&2) designed to operate at 4K inside the dilution refrigerator.

Stefano Pellerano received the Laurea Degree and the Ph.D. degree in electronics engineering from the Politecnico di Milano, Milan, Italy, in 2000 and in 2004, respectively. Since 2004 he has been with Intel Labs, in Hillsboro, OR. He is now Principal Engineer leading the Next Generation Radio Integration Lab, where he drives several research activities focused at enabling radio circuit integration in deeply-scaled CMOS technologies. In the last five years, he has also been exploring cryogenic CMOS integrated electronics for qubit control, leading to the development of “Horse Ridge”, Intel cryogenic qubit controller technology to address the interconnect bottleneck in future large-scale quantum computers. He was a co-recipient of ISSCC 2019 Lewis Winner Award for Outstanding Paper and ISSCC 2020 Jan Van Vessem Award for Outstanding European Paper. He served as a member of the ISSCC iTPC from 2014 to 2022, leading the Wireless Subcommittee from 2018 to 2022. He is currently serving as the Forum Chair for 2023 ISSCC. He also served as the Technical Program Chair and General Chair for the IEEE Radio Frequency Integrated Circuit (RFIC) Symposium in 2018 and 2019 respectively and he is now part of the RFIC Executive Committee.