FPGA Demo
Session Chair: Chuen-Yau Chen, National University of KaohsiungDate: Nov. 07, 2022 (Monday)
Time: 14:00 – 17:40 (UTC+8)
Room: Sky Lounge 崑崙廳, 12F
| ID | Time | Title / Authors / Affiliation |
| FPGA1 (7254) (On-site) |
14:00 | 17:40 |
A 75.6M Base-pairs/s FPGA Accelerator for FM-index
Based Paired-end Short-Read Mapping Chung-Hsuan Yang1, Yi-Chung Wu1, Yen-Lung Chen1, Chao-Hsi Lee2, Jui-Hung Hung2,3, Chia-Hsiang Yang1,2 1National Taiwan University, Taiwan 2GeneASIC Technologies Corp., Taiwan 3National Yang Ming Chiao Tung University, Taiwan |
| FPGA2 (7152) (On-line) |
14:00 | 17:40 |
A 217.8 MSOPs/W FPGA-based Online Learning SNN
Processor Using Unified Event-Driven Structure and
Topology Aware Data Reuse Strategies Chaoming Fang1,2, Fengshi Tian2, Chuanqing Wang2, Jie Yang2, Mohamad Sawan2 1Zhejiang University, China 2CenBRAIN Neurotech, Westlake University, China |
| FPGA3 (7187) (On-line) |
14:00 | 17:40 |
A Flexible Instruction-based Post-quantum Cryptographic Processor with Modulus Reconfigurable
Arithmetic Unit for Module LWR&E Aobo Li, Dongsheng Liu, Xiang Li, Tianze Huang, Shuo Yang, Jiahao Lu, Ang Hu Huazhong University of Science and Technology, China |
| FPGA4 (7100) (On-line) |
14:00 | 17:40 |
Method of Halved Interaction Elements with Regularity
Arrangement that achieves Independent Double Systems
for Scalable Fully Coupled Annealing Processing Shinjiro Kitahara, Akari Endo, Taichi Megumi, and Takayuki Kawahara Tokyo University of Science, Katsushika, Japan |
| FPGA5 (7217) (On-site) |
14:00 | 17:40 |
A Real-Time High-Resolution Variable-Size Imaging
Processor for Spaceborne Synthetic Aperture Radar Jia-Zhao Lin1, Po-Ta Chen1, Hung-Yuan Chin1, Pei-Yun Tsai1, and Sz-Yuan Lee2 1National Central University, Taiwan 2National Applied Research Laboratory, Taiwan |
| FPGA6 (7239) (On-site) |
14:00 | 17:40 |
A 409.6 GOPS and 204.8 GFLOPS Mixed-Precision Vector
Processor System for General-Purpose Machine Learning
Acceleration Jung-Hoon Kim, Sukjin Lee, Seungjae Moon, Sungyeob Yoo, and Joo-Young Kim KAIST, Korea |
| FPGA7 (7248) (On-site) |
14:00 | 17:40 |
An Efficient Unsupervised Learning-based Monocular
Depth Estimation Processor with Partial-Switchable
Systolic Array Architecture in Edge Devices Wonhoon Park, Dongseok Im, Hankyul Kwon, and Hoi-Jun Yoo Korea Advanced Institute of Science and Technology, Korea |
| FPGA8 (7235) (On-line) |
14:00 | 17:40 |
F-LIC: FPGA-based Learned Image Compression with a
Fine-grained Pipeline Heming Sun1,2,3, Qingyang Yi4, Fangzheng Lin1, Lu Yu2, Jiro Katto1, and Masahiro Fujita4,5 1Waseda University, Japan 2Zhejiang University, China 3JST, PRESTO, Saitama, Japan 4The University of Tokyo, Japan 5AIST, Japan |