RF, mmW and subTHz : Trends and the Outlook Towards 6G

• Jon Strange
• • MediaTek, UK

• Date: November 08, 2022 (Tuesday)
• Time: 16:00 - 16:20 (UTC+8)
• Room: Auditorium 國際會議廳, 10F

With the goal of deployment around 2030 researchers and companies worldwide are turning their attention to the development of the next generation mobile networks namely 6G. Key goals, from the 5G/5G-Advanced baseline will be improvements in latency, reliability and energy efficiency while also increasing the typical data rates experienced by users. This presentation will discuss the evolving need of the RF semiconductor technologies starting from the baseline of today’s 5G state of the art. Specific emerging 6G technologies such as sub-THz and gigantic MIMO systems, will be discussed from a RF technology perceptive and the availability of global radio frequency spectrum.

Jon is a MediaTek Fellow and Senior Director currently responsible for corporate technology research strategy. Previous to this he ran the design team responsible for MediaTek’s cellular transceivers and during a 35 year career has developed products for all the G’s from initial analog cellular to current mmWave transceivers shipping over 2B cumulative units. Prior to MediaTek he ran the UK RF design centre of Analog Devices after the acquisition of Mosaic Micosystems in 1996 a company which he co-founded. He is a graduate of Durham and Edinburgh Universities and lives and works in the UK.

Attack-Resistant Cryptographic Circuit Technologies for sub-5nm Secure Computing Platforms

• Sanu Mathew
• • Intel, USA

• Date: November 08, 2022 (Tuesday)
• Time: 16:20 - 16:40 (UTC+8)
• Room: Auditorium 國際會議廳, 10F

Cryptographic hardware accelerators and root-of-trust circuits have become essential components of present-day secure platforms. These circuits provide an on-die boundary within which users are given assurances that data privacy and integrity is preserved during computations and transport between storage and compute elements. The focus of hardware security engineers over the past many years has been in improving performance while reducing area and power consumption of cryptographic circuits. This tidy scenario was disrupted by a spate of attacks on computing platforms reported in the past few years. These attacks employed techniques such as speculative side-channels, physical (power/electromagnetic) side-channels, voltage/clock glitching and fault-injection to extract embedded secrets such as encryption keys or access privileged sections of system memory. The security community has responded to these attacks by launching research in resilient architectures and security circuits that are resistant to physical/machine-learning attacks. This talk will discuss attack-resistant encryption circuits for popular encryption workloads such as AES and RSA as well as describe PUF circuits that are resilient to powerful machine-learning attacks. While these circuits are shown to be secure against known attacks today, attackers are getting increasingly sophisticated with high resolution probes and employing advanced machine-learning techniques to subvert protection mechanisms. Security hardware designers are therefore engaged in an arms race of constantly outwitting malicious attackers while relying on continued research in energy-efficient attack-resistant security circuits.

Sanu Mathew is a Senior Principal Research Scientist with the Circuits Research Labs, Intel Corporation, where he is leads the security circuits research team. His research work focuses on energy-efficient arithmetic data-paths, side-channel resistant cryptographic HW accelerators, post-quantum crypto circuits, fully-homomorphic-encryption hardware and entropy generation circuits. He received his Ph.D. degree in Electrical Engineering from State University of New York at Buffalo in 1999. He holds 111 patents and has authored 97 conference/journal publications. Sanu is a Fellow of the IEEE.

General-purpose scalar/vector AI processor for accelerating wide range of tasks including automotive and industrial applications

• Masayuki Ito
• • NSITEXE Inc, Japan

• Date: November 08, 2022 (Tuesday)
• Time: 16:40 - 17:00 (UTC+8)
• Room: Auditorium 國際會議廳, 10F

Efficient execution of AI and other computing on edge devices has become an important issue in embedded systems due to strict heat and cost constraints. In this talk, a solution and techniques being explored to efficiently accelerate the computation of wide range of contributions to the embedded systems will be covered. More specifically, scalable solutions for each application by combining versatile MIMD-based processors with vector units will be introduced. Both task-level parallelism and data-level parallelism are fulfilled by the MIMD-based processors and the vector units, and tight coordination of them are key to efficient execution contribution.

Dr. Masayuki Ito is Director in Business Promotion Unit at NSITEXE Inc, Denso's subsidary, where he focuses on business promotions for its own RISC-V processor and AI accelerators. He has more than 20 years of experience in the semiconductor industry. He started his career in the Semiconductor Development Center in Hitachi Ltd. in Tokyo, followed by Renesas Technology Corp. and Renesas Electronics Inc. Throughout his career he consistently worked for processor and SoC development for mobile and automobile. He holds a master's degree in Computer engineering from Kyoto University and a Ph.D. in Science and Engineering from Tokyo Institute of Technology in Japan.

Key technologies for smart vision sensors

• Hayato Wakabayashi
• • Sony, Japan

• Date: November 08, 2022 (Tuesday)
• Time: 17:00 - 17:20 (UTC+8)
• Room: Auditorium 國際會議廳, 10F

Today, the performance of CMOS image sensors exceeds the capabilities of the human eye and can provide more immersive experiences as a result. In addition, the image sensors for sensing can digitize various other kinds of information than typical 2-dimensional images where applications such as authentication, recognition, autonomous machine control, and wireless products further process this useful and efficient information. These latest vision sensors enhance the quality of services and the evolution of image sensing systems grow into a broader information conversion tool.

In this talk, the requirements and use-cases for smart vision sensors will be discussed. The key technologies and performance of event-driven sensors for computer vision applications, event-based sensors for industrial automation, and intelligent vision sensors for smart city will be demonstrated. Finally, our vision of how the upcoming combination of Smart Vision Sensors and Artificial Intelligence technologies will profoundly influence our lifestyle will be introduced.

Hayato Wakabayashi is a deputy General Manager of Research Division at Sony Semiconductor Solutions Corporation. He received a M.S in the Engineering from Osaka University and Ph.D. from Tohoku University, Japan respectively. He served on the technical program committee of the symposium on VLSI Circuits from 2014 to 2017 and had been engaged in a member of the technical program committee of International Solid-State Circuits Conference from 2017 to 2021. And he received the Walter Kosonocky Award for the paper of back-illuminated CMOS image sensor in 2011. He is currently working on the research and development of future imaging and sensing devices, low power circuits and AI systems.

Next-Generation DRAM Solution for HPC and AI

• Kyomin Sohn
• • Samsung, Korea

• Date: November 08, 2022 (Tuesday)
• Time: 17:20 - 17:40 (UTC+8)
• Room: Auditorium 國際會議廳, 10F

The strong demand for computing power from the industry, which began with big data and AI applications, is evolving from a new memory hierarchy to a domain specific solution. It includes LLC(Last Level Cache) memory using DRAM cell technology, PIM(Processing-in-Memory) for reducing data movement, HBM DRAM for higher bandwidth, and CXL-DRAM solutions for higher capacity and connectivity. Especially, HBM-PIM solution will be discussed in detail.

Kyomin Sohn received the B.S. and M.S. degrees in Electrical Engineering in 1994 and 1996, respectively, from Yonsei University, Seoul. From 1996 to 2003, he was with Samsung Electronics, Korea, involved in SRAM Design Team. He designed various kinds of high-speed SRAMs. He received the Ph.D. degree in EECS in 2007 from KAIST, Korea. He rejoined Samsung Electronics in 2007, where he has been involved in DRAM Design Team. He is a Master (VP of Technology) in Samsung and he is responsible for future architecture and circuit technology of DRAM. His interests include 3D-DRAM, reliable memory design, and processing-in-memory. In addition, he has currently served as a Technical Program Committee member of Symposium on VLSI Circuits since 2012.