From Si-Soft to Å Semiconductor- the IT Vision in Taiwan

• Chen-Yi Lee
• • National Yang Ming Chiao Tung University, Taiwan

• Date: November 07, 2022 (Monday)
• Time: 10:50 - 11:15 (UTC+8)
• Room: Song Bo 松柏廳, 10F

Enhance core-competence and create more job opportunities remain the same vision for any government when budgets are allocated for specific national program (NP) or initiative in high-tech policy making. In this talk, we will first introduce the policy-making for semiconductor industry-chain in Taiwan, including end-point and annual milestones. Then the promotion of the government-funded NP at different Ministries and project execution of selected research teams will be highlighted to evaluate the NP progress with predefined objectives and key results (OKR). We will use both Si-Soft (2002/12) and A-Semiconductor(2020/12) NP’s to illustrate how to reach each individual endpoint with different strategies by taking into account different factors, such as geopolitical challenge, global climate change, and supply-demand unbalance of talent pools. In the end, some statistical datasets and successful stories will be provided to evaluate the NP outcome, especially the impact to the continuous growth of semiconductor industry.

Chen-Yi Lee received the Ph.D. degree in electrical engineering from Katholieke University Leuven (KUL), Belgium in 1990. He is currently a Professor in the Institute of Electronics and serves as Senior Vice President of National Yang Ming Chiao Tung University (NYCU), Taiwan. His research interests mainly include VLSI algorithms and architectures for high-throughput DSP and Data-Driven applications. He is also active in various aspects of micro sensing, low-power system-on-chip, and machine learning.

He holds more than 50 US patents and co-founded 4 startups related to data-driven applications.

The Era of Agile and Open-Source Hardware

• Yungang Bao
• • Institute of Computing Technology (ICT), China

• Date: November 07, 2022 (Monday)
• Time: 11:15 - 11:40 (UTC+8)
• Room: Song Bo 松柏廳, 10F

Agile and open-source hardware design is considered to be one of the most promising ways to lower the design cost of chip design. In this Talk, I will introduce two projects towards the era of agile and open-source hardware: 1) XiangShan is an open-source high-performance RISC-V processor project started in June 2020. The first generation of XiangShan was taped-out at a frequency of 1.3GHz on 28-nm CMOS process in July 2021, which achieved a score of 7/GHz on SPECCPU 2006. The second generation of XiangShan targets 2GHz on 14-nm CMOS process, achieving a score of 10/GHz on SPECCPU 2006. XiangShan is developed in Chisel, using many new open-source agile tools. 2) The One Student One Chip (OSOC) Initiative was launched in 2019, aiming to instruct undergraduates to build real chips. Five undergraduates participated in the OSOC Initiative and completed a 64-bit RISCV processor SoC, which was manufactured by 110nm technology and can successfully run Linux at 200MHz. By now, more than 2000 students of 230 universities applied to participate in the OSOC Initiative.

Yungang Bao is a professor of Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS) and the deputy director of ICT, CAS. Prof. Bao founded China RSIC-V Alliance (CRVA) and serves as the secretary-general of CRVA. His research interests include computer architecture and computer systems. He is leading the XiangShan project, which aims to build an open-source high performance RISC-V core. He launched the One Student One Chip (OSOC) Initiative in 2019, which trains undergraduates to build real chips and has already attracted about 1800 participants from 200+ universities. His prior research works such as Labeled von Neumann Architecture (LvNA), Hybrid Memory Trace Tool (HMTT), Partition-Based DMA Cache and PARSEC 3.0 have been adopted by the industry including Alibaba, Huawei, Intel, Microsoft and also published on top conferences and journals such as ASPLOS, Communication of the ACM, HPCA, ISCA, NSDI and SIGCOMM etc. He was invited to present plenary keynote speeches at China National Computer Congress (CNCC) in 2016 and at ARM Research Summit 2018. He was the winner of CCF-Intel Young Faculty Award of the year for 2013 and the winner of CCF-IEEE CS Young Computer Scientist Award and China’s National Lofty Honor for Youth under 40 of the year for 2019.

New waves of semiconductor for future AI pervasive era

• Hyun-Kyu Yu
• • ETRI, Korea

• Date: November 07, 2022 (Monday)
• Time: 11:40 - 12:05 (UTC+8)
• Room: Song Bo 松柏廳, 10F

As the scaling of semiconductor technology is actually coming to an end, manufacturing costs are skyrocketing. Meanwhile, after the successful events in 2012 and 2016, AI is now entering a full-fledged renaissance period, and its application continues to expand from deep learning-based vision recognition to fields that require huge AI computing resources such as NLP. Sooner or later, it seems that we will enter a phase where we are faced with serious decoupling between HW (traditional semiconductor) and SW (new coming AI algorithm). This means that we have come to an era similar to the situation in which the limitations of vacuum tube-based ENIAC in the 1940s invoked silicon semiconductors.

Meanwhile, various market research institutes are predicting that the demand for AI edge will increase significantly in the future, and 6G, which will come soon, is expected to be another huge opportunity for AI. Indeed, 6G is the realization of global network intelligence. The emergence of new semiconductor devices with high energy efficiency is urgently needed. How will you bridge the gap between supply and demand until new devices appear ? Advanced packaging technologies such as chiplet are entering the mainstream, data (or memory)-centric computing is attracting attention, and open platforms that can manage various AI functions and services in an integrated way are emerging. Also, the semiconductor itself is a time when a paradigm shift is required to intelligently reconfigure and adapt to a diverse and dynamic world just like humans have survived.

Hyun-Kyu Yu (M’94-SM’01) received the B.S. and M.S. degrees in electronics engineering from Kyungpook Nat’l University in 1981 and 1983 respectively, and the Ph.D. degree in electrical and electronics engineering from KAIST in 1994. In 1983, he joined the ETRI, where he worked on both 4M/16M/64M DRAM Nat’l project, SOI MOSFET modeling, and standard cell library. Since 1996, he has led RF/Analog IC design team that successfully developed the world first CMOS based Rx/Tx chips for the CDMA and PCS cellular phone in 1999 and 2001 respectively. Since 2006, he has been the director of mm-wave group which developed mm-wave and optical devices, circuits, and systems with heterogeneous packaging technologies. He also served as a senior vice president with the responsibility of developing SW-SoC convergence technologies during 2012 ~2013. More recently, he is engaging in the role of Nat’l planning that builds up strategies for AI semiconductor competitiveness and industrial eco-system. He is also now teaching neuromorphic devices and circuits course as a visiting professor of Chungnam Nat’l university since 2021. Dr. Yu was a president of ISE (Institute of Semiconductor Engineering) in 2019, and a senior member of IEEE since 2001. He founded and has been serving as chairman of the RF Integrated Circuit Technology Society in Korea during 2000~2013. He has received several awards including Nat’l medal for the contribution of system on chip technologies and its related eco-system. He is the author and co-author of over 120 technical papers and 100 patents in the devices, circuits, and system design areas.

Democratize chip design

• Makoto Ikeda
• • The University of Tokyo, Japan

• Date: November 07, 2022 (Monday)
• Time: 12:05 - 12:30 (UTC+8)
• Room: Song Bo 松柏廳, 10F

Japanese Ministry of Education(MEXT) has initiated a 10-year project named X-nics, and selected 3 universities as the hub site, one of which is the University of Tokyo, in a title of "Agile-X: Democratizing platform for innovative semiconductor technology." This talk will cover the basic concept of this Agile-X platform, along with other government initiated research project in circuit designs.

Makoto Ikeda received the BE, ME, and Ph.D. degrees in electrical engineering from the University of Tokyo, Tokyo, Japan, in 1991, 1993 and 1996, respectively. He joined the University of Tokyo as a research associate, in 1996, and now professor at d.lab, the University of Tokyo. He is also the professor at department of electrical engineering and information systems, graduate school of engineering, the University of Tokyo. He stayed in Cambridge University as a visiting Researcher in 2001-2001. He has been involving the activities of VDEC to promote VLSI design educations and researches democratization in Japanese academia. And now initiated “AI chip design project” for Japanese startups, supported by Ministry of Economy, Trade and Industry (METI) of Japan. His research topics including hardware security, smart image sensor for 3-D range finding, and time-domain circuits including asynchronous controlling and associate memories.

He served conference organizations, including ISSCC 2021 Program Chair, VLSI Symposium 2017 Program Chair, A-SSCC 2015 Program Chair, and various conferences as a program committee member. He served as a Distinguished Lecturer of IEEE SSCS for 2015 and 2016, Elected AdCom member for 2020-2022. He is a senior member of IEEE, a senior member of IEICE, and a member of ACM and IPSJ.