CICC Joint Session


A 112 Gb/s -8.2 dBm Sensitivity 4-PAM Linear TIA in 16nm CMOS with Co-Packaged Photodiodes


  • Dhruv Patel
    • University of Toronto

  • Date: November 09, 2022 (Wednesday)
  • Time: 11:00 - 11:20 (UTC+8)
  • Room: Chang Chin 長青廳, 10F

Abstract:

Low-cost optical receivers (RX) operating at 100+ Gb/s 4-PAM with low power are in high demand to support 400GBASE-DR4/FR4 links in data centers. Existing pluggable solutions generally realize the RX front-end in BiCMOS. However, a more integrated solution, with the RX front-ends integrated onto a CMOS host IC and co-packaged alongside the photodiodes (PDs), offers the potential for smaller size, lower cost, and lower power [1], [2]. This work demonstrates a 112 Gb/s 4-PAM linear TIA in CMOS flip-chip co-packaged with commercial PDs and different PD-to-RX interconnect lengths.


Biography:

Dhruv Patel (S’12) received BASc. and MASc. degrees in Electrical Engineering from the University of Waterloo and the University of Toronto in 2016 and 2020, respectively. He was involved with variation tolerant sub-threshold SRAM circuits research during undergraduate studies. Since 2019, he is pursuing his PhD. at the University of Toronto with Integrated Systems Laboratory working towards Optical Communication Links in CMOS. He was the recipient of the outstanding student paper award at Custom Integrated Circuits Conference 2022. He has received Ontario Graduate Scholarship and NSERC scholarship for his doctoral studies.





A 20μs turn-on time, 24kHz resolution, 1.5-100MHz digitally programmable temperature-compensated clock generator with 7.5ppm/°C inaccuracy

  • Yongxin Li
    • University of Illinois at Urbana-Champaign

  • Date: November 09, 2022 (Wednesday)
  • Time: 11:20 - 11:40 (UTC+8)
  • Room: Chang Chin 長青廳, 10F

Abstract:

The demand for portable electronic devices with a small form factor and extended battery life is ever increasing. Timing circuits impose several critical impediments in meeting this demand. For example, low-power microcontroller units use multiple crystal oscillators (XOs) and several on-chip fractional-N phase-locked loops (PLLs) to generate the desired clocks, which significantly increase board space, power consumption. XOs and PLLs cannot be turned ON and OFF rapidly, so they also severely limit the ability to employ system-level power-reduction strategies such as power cycling. On-chip closed-loop frequency-locked loop (FLL) based oscillators are promising candidates to address some of these drawbacks [1]. While they can achieve excellent frequency accuracy, they occupy a large area, consume significant power, and cannot be turned ON/OFF rapidly due to their very low bandwidth and can only provide an output at one fixed frequency. Given these drawbacks, this paper presents a fast start-up, temperature-stable digital FLL-based oscillator and low jitter open-loop fractional dividers that can provide highly programmable clock outputs. Fabricated in a 65nm CMOS process, the prototype can generate clock outputs from about 1.5MHz to 100MHz with a frequency inaccuracy and resolution of 7.5ppm/°C and 24kHz, respectively.


Biography:

Yongxin Li received the B.S. and M.S. degrees in electrical and computer engineering from the University of Illinois at Urbana–Champaign, Urbana, IL, USA, in 2017 and 2020, respectively, where he is currently pursuing the Ph.D. degree. He was an intern with the silicon photonics link group, Cisco in 2019 and 2020, and was with the FPD link group, Texas Instruments in 2021, respectively. His research interests include clocking circuits and high-speed links.





A 23-37GHz Autonomous Two-Dimensional MIMO Receiver Array with Rapid Full-FoV Spatial Filtering for Unknown Interference Suppression

  • Boce Lin
    • Georgia Institute of Technology

  • Date: November 09, 2022 (Wednesday)
  • Time: 11:40 - 12:00 (UTC+8)
  • Room: Chang Chin 長青廳, 10F

Abstract:

Due to the rapid growth in wireless mobile devices use (e.g., autonomous vehicles and unmanned aircraft systems), there is a rising demand for high-speed/Multiple-Input-Multiple-Output (MIMO) wireless links to navigate the increasingly dynamic environments. Current mm-Wave links rely on large transmitting/receiving (Tx/Rx) digital arrays to support the required mm-Wave link budget at the cost of narrower communication beamwidth, which demands fine beam alignment over the entire field-of-view (FoV), increases the number of iterations required to establish a reliable link, and worsens the overall array's response time. Agile and rapid spectral-spatial front-end filtering/beamforming is required to facilitate wideband mm-Wave digital arrays to handle varying strong blocker signals with unknown frequency/angle-of-arrival (AoA) in practical EM scenarios. Most existing front-end spatial filtering methods in digital arrays use open-loop analog beamformers [1]–[3], which have limited FoV, require previous knowledge (frequency/AoA) of the signals/blockers or perform on-the-fly beam-space computations using digital backends which is not suitable for mobile applications. An alternative to FoV-limited analog front-end beamforming is utilizing the digital backend to identify the blockers'/signals' AoA and applying the optimum spatial filtering and beamforming in response [4]. The presence of multiple strong signals/blockers imposes high linearity and high dynamic range requirements on the receiver front-end and ADC; otherwise, strong signals/blockers may saturate the front-end, and exceed the ADC dynamic range. A DLL-like autonomous beamformers using phase-domain negative feedback is reported in [5] which rapidly suppresses multiple unknown strong signals or blockers and support wideband Gbit/s signals/blockers [5]. However, its array architecture only demonstrates 1–D array operation and cannot handle practical applications in a planar 2-D array.


Biography:

Boce Lin received his B.S. degrees from Southern Methodist University and M.S. degrees from Georgia Institute of Technology in 2019 and 2021. He is currently a Ph.D candidate at ETH Zurich. His research interests are including mm-Wave Transceiver systems and Cryogenic CMOS circuits and systems. 





An 0.92 mJ/frame High-quality FHD Super-resolution Mobile Accelerator SoC with Hybrid-precision and Energy-efficient Cache

  • Zhiyong Li
    • KAIST

  • Date: November 09, 2022 (Wednesday)
  • Time: 12:00 - 12:20 (UTC+8)
  • Room: Chang Chin 長青廳, 10F

Abstract:

With the rise of contactless communication and streaming services, Super-resolution (SR) in mobile devices has become one of the most important image processing technologies. Also, The popularity of high-end Application Processor (AP) and high resolution display in mobile drives the development of the lightweight mobile SR-CNNs [1], [2], which show the high reconstruction quality. However, the large size and wide dynamic range of both images and intermediate feature maps in CNN hidden layers pose challenges for mobile platforms. Constraints from the limited power (<100mW) and shared bandwidth (<2GB/s) on mobile platform, a low power and energy-efficient architecture is required.


Speaker's Biography:

(on behalf of Zhiyong Li)
Sangjin Kim (Student Member, IEEE) received the B.S. degrees in electrical engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea, in 2019, and the M.S. degree in electrical engineering from the KAIST in 2021, where he is currently pursuing the Ph. D. degree. His current research interests include intelligent 3D vision SoC, low-power system-on-chip design for deep neural network accelerator, processing-in-memory for efficient machine learning system. Contact him at sangjinkim@kaist.ac.kr.





A 3.8-dB NF, 23-40GHz Phased-Array Receiver with 14-Bit Phase & Gain Manager and Calibration-Free Dual-Mode 28-52dB Image Rejection Ratio for 5G NR

  • Zhixian Deng
    • University of Electronic Science and Technology of China

  • Date: November 09, 2022 (Wednesday)
  • Time: 12:20 - 12:40 (UTC+8)
  • Room: Chang Chin 長青廳, 10F

Abstract:

The ever-increasing demands on the high data-rate and high signal-to-noise ratio accelerate the development of high-performance millimeter-wave phased-array systems, especially for 5G NR at 24, 28, 37, and 39GHz bands. However, the reports of the wideband phased-array receiver (RX) [1]–[6] that can fully cover the 24/28/37/39 GHz bands are limited. The suppression of image-signal located at the RF passband is the main challenge for such wideband RX array. Meanwhile, the phase resolution and dynamic range of the phased-array RX should be improved to support multiple applications. This work presents a 23-40GHz phased-array RX in a 40-nm CMOS technology. The proposed phased-array RX consists of a 14-bit phase & gain manager and a noise-cancelling low noise amplifier (LNA). The phase & gain manager with the capacity of rearranging the phase- and gain-control bit can not only provide a maximum 14-bit phase tuning operation and >35dB gain variation range, but also achieve a 28-52dB calibration-free image rejection ratio (IRR) at 23-40GHz by the dual-mode operation. The fabricated chip can support 3Gb/s, 64-QAM and 2.4Gb/s, 256-QAM modulation signal.


Biography:

Zhixian Deng received the B.E. degree in microelectronics science and engineering from the University of Electronic Science and Technology of China, Chengdu, China, in 2019, where he is currently pursuing the Ph.D. degree in electronic science and technology. His research interests include the reconfigurable microwave/millimeter-wave transceiver and passive components, especially integrated circuits.

Mr. Deng was a recipient of the IEEE International Microwave Symposium (IMS) Student Design Competition Award from 2017 to 2019 and the 2022 IEEE Microwave Theory and Techniques (MTT)-Society Graduate Fellowship Award. He serves as a reviewer of IEEE Microwaves and Wireless Component Letter, IEEE Transaction on Microwave Theory and Techniques, IEEE Transaction on Circuits and Systems-I: Regular Paper, and IET Microwaves, Antennas & Propagation.




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